This inventor holds 1 USPTO granted patent. Top assignee: Cypress Semiconductor Corporation. Active years: 2002.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2002
Title: Kailash Nagarakanti and Flexible Counter Logic for Memory Configuration.
Introduction
Kailash Nagarakanti is an inventor associated with Santa Clara, California, and Cypress Semiconductor Corporation. His patent work includes a counter-logic design intended to support flexible configuration of memory systems.
Latest Patents
Nagarakanti is named on the patent “Counter Logic for Multiple Memory Configuration.” The invention describes a system and method for selectively masking counter output bits by modifying the carry chain. Its components include a mask register, a counter, and a masking coordination circuit. When a mask bit is not asserted, the circuit allows the carry-in, carry-out, and counter output to operate normally. When the mask bit is asserted, it prevents the corresponding counter output bit from changing, enabling programmable control of multiple memory configurations. The supplied information lists 1 patent for Nagarakanti.
Career Highlights
Nagarakanti’s listed work connects digital counter logic with memory configuration. The patent’s approach uses selective masking to adapt counter behavior for different memory arrangements.
Collaborations
The supplied information identifies Cypress Semiconductor Corporation as Nagarakanti’s company and William G. Baker as a coworker.
Conclusion
Kailash Nagarakanti’s patent describes a flexible counter-masking technique designed to support programmable memory configurations.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile