Zhubei, Taiwan

Kaihong Wang

This inventor holds 1 USPTO granted patent. Top assignee: Silicon Motion, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kaihong Wang. Retrieved from https://idiyas.com/inventor/kaihong-wang-6va35i4c

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Kaihong Wang and Flash Memory Controller Innovation.

Introduction

Kaihong Wang is an inventor associated with Zhubei, Taiwan. His work includes a patent on accelerating logical-to-physical address lookups in a symmetric multiprocessing environment, with an application to flash memory controllers.

Latest Patents

Wang is credited with 1 patent: “Method for Accelerating Logical-to-Physical Address Lookup Operations in Symmetric Multi-Processing Environment and Flash Memory Controller Using the Same.”

The invention describes a memory controller with multiple processor cores and a lookup acceleration circuit. Its message processing circuit receives requests through request queues and places an incoming request in a collision pending queue when its logical address range conflicts with ranges associated with active requests. A mapping-table lookup circuit converts the active requests’ logical address ranges into physical addresses using a table stored in volatile memory. The controller then uses those addresses to perform the corresponding memory-access operations.

Career Highlights

Wang is associated with Silicon Motion, Inc., a company that develops memory and storage solutions. His patent focuses on coordinating concurrent requests and accelerating address translation in flash memory systems.

Collaborations

Cheng Yi is identified as Wang’s coworker. The available information does not specify whether Yi collaborated on the patent.

Conclusion

Kaihong Wang’s patent addresses a key memory-controller challenge by coordinating conflicting requests and accelerating logical-to-physical address lookups for flash memory operations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…