Kai-Jun Chang

Title: Innovations by Inventor Kai-Jun Chang

Introduction

Kai-Jun Chang is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor packaging, particularly in testing methods for multi-chip stacked packages. With a total of 2 patents, his work has advanced the efficiency and effectiveness of testing processes in this technology sector.

Latest Patents

Chang's latest patents include a method for testing multi-chip stacked packages and a method for wafer-level testing diced multi-chip stacked packages. The first patent discloses a method that involves providing substrate-less chip cubes, adhering them onto adhesive tape, and forming a filling encapsulant to facilitate testing. This innovative approach allows for easy integration into TSV fabrication processes. The second patent outlines a method for wafer-level testing, where multi-chip stacked packages are fixed on a transparent reconstructed wafer using a photo-sensitive adhesive. This method enhances the probing capabilities of wafer testing probers, making it particularly useful in TSV packaging processes.

Career Highlights

Kai-Jun Chang is currently employed at Powertech Technology Inc., where he continues to develop and refine testing methods for semiconductor technologies. His expertise in this area has positioned him as a key figure in advancing industry standards and practices.

Collaborations

Chang has collaborated with notable colleagues such as Yu-Shin Liu and Shin-Kung Chen. Their combined efforts contribute to the innovative advancements in semiconductor packaging and testing methodologies.

Conclusion

In summary, Kai-Jun Chang's contributions to the field of semiconductor testing through his innovative patents and collaborations have significantly impacted the industry. His work continues to pave the way for advancements in multi-chip stacked package testing methods.