Kadiri R Reddy

Title: Innovations of Kadiri R Reddy

Introduction

Kadiri R Reddy is a notable inventor based in Santa Clara, California. He has made significant contributions to the field of digital arithmetic through his innovative patent. His work focuses on enhancing the efficiency of floating point arithmetic in digital multipliers.

Latest Patents

Kadiri R Reddy holds a patent for a "Round off correction logic for modified Booth's algorithm." This invention discloses a round off correction logic circuit designed for inclusion within a floating point arithmetic binary digital multiplier. The circuit implements a modified Booth's algorithm to generate a final product of binary digits. The round off logic circuitry is connected in the multiplier to round its final product off to a predetermined binary digit. This process eliminates the need for the multiplier to generate any less significant binary digits to the right of the predetermined binary digit. Consequently, multiplier circuitry that would typically be required to generate an unrounded final product prior to round off is eliminated, all without sacrificing accuracy in the round off process.

Career Highlights

Kadiri R Reddy is currently employed at American Microsystems, Inc., where he continues to innovate in the field of digital technology. His work has been instrumental in advancing the capabilities of digital multipliers, making them more efficient and accurate.

Collaborations

One of his notable coworkers is Roubik Gregorian, with whom he collaborates on various projects within the company.

Conclusion

Kadiri R Reddy's contributions to the field of digital arithmetic through his innovative patent demonstrate his expertise and commitment to advancing technology. His work continues to influence the development of efficient digital multipliers.