Hyderabad Telangana, India

Jyothi Ramidi

USPTO Granted Patents = 2 

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2025

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2 patents (USPTO):Explore Patents

Title: Jyothi Ramidi: Innovator in Memory Data Integrity

Introduction

Jyothi Ramidi is a notable inventor based in Hyderabad, Telangana, India. She has made significant contributions to the field of memory data integrity, holding 2 patents that focus on enhancing performance and reliability in memory systems. Her work is particularly relevant in today's technology-driven world, where data integrity is paramount.

Latest Patents

Jyothi's latest patents include "Apparatus and methods for memory data integrity within die architectures" and "Partial row refresh in a memory device." The first patent addresses methods and apparatuses aimed at improving performance and data integrity within die architectures. It describes a system where a memory device serves as a cache for another memory device, allowing a processor to manage error detection and data storage efficiently. The second patent provides systems and methods for supporting partial row refresh operations in memory systems, enhancing the efficiency of memory array management.

Career Highlights

Jyothi Ramidi is currently employed at Qualcomm Incorporated, a leading technology company known for its innovations in telecommunications and semiconductor technology. Her role at Qualcomm allows her to work on cutting-edge technologies that impact various aspects of modern computing.

Collaborations

Throughout her career, Jyothi has collaborated with talented individuals such as Subham Panda and Muzaffaruddin Mohammed. These collaborations have likely contributed to her innovative work and the successful development of her patents.

Conclusion

Jyothi Ramidi stands out as an influential inventor in the realm of memory data integrity. Her patents reflect her commitment to advancing technology and improving data reliability in memory systems. Her contributions are vital in shaping the future of memory architecture and performance.

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