Qualcomm Incorporated

Jyothi Ramidi

Subham Panda

Venkatesh Petnikota

Sri Ananda Sai Jannabhatla

Muzaffaruddin Mohammed

Radhakrishna Mugada

Nileshkumar Chandrakantbhai Motawala

Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Apparatus and methods for memory data integrity within die architectures

This disclosure provides systems, methods, and devices for memory systems that support partial row refresh operation of a memory system. In a first aspect, a method of refreshing a memory array includes obtaining, by a memory controller from a host device through a channel, partial row refresh information associated with a first row in a memory array and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information. Other aspects and features are also claimed and described.

Partial row refresh in a memory device

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Hyderabad Telangana, India

Jyothi Ramidi