Suwon, South Korea

Jun-bum Lee

This inventor holds 2 USPTO granted patents and 1 EPO patent. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jun-bum Lee. Retrieved from https://idiyas.com/inventor/jun-bum-lee-pww815zs

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile



Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Jun-bum Lee: Innovator in Semiconductor Memory Devices

Introduction

Jun-bum Lee is an inventor based in Suwon-si, South Korea. He is known for his work in the field of semiconductor memory devices. Although he currently holds no granted patents, his innovative ideas are reflected in his latest patent applications.

Latest Patent Applications

Jun-bum Lee has submitted several patent applications related to semiconductor memory devices. One of his applications describes a semiconductor memory device that features active regions defined by a device isolation layer on a substrate. This design includes a word line that crosses the active regions, along with a gate dielectric layer positioned between the word line and the active regions. Additionally, a capping insulating pattern covers the upper surface of the word line, and a bit line is placed on top of the word line. The word line may consist of a first conductive pattern and a second conductive pattern, where the first conductive pattern includes a first metal element. The second conductive pattern incorporates the first metal element, a work function adjustment element, and a diffusion barrier element, with the atomic radius of the diffusion barrier element being smaller than that of the first metal element.

Another application focuses on a semiconductor memory device that includes a semiconductor substrate with a device isolation trench defining active regions. This device features a device isolation layer within the trench, gate trenches extending in a first direction, and word lines positioned in the gate trenches. The design specifies that the first trench sections in the active regions have a first depth, while the second trench sections in the device isolation layer have a greater second depth. The device isolation layer is composed of a lower portion that is positioned lower than the bottom surfaces of the first trench sections and an upper portion on top of the lower portion. The lower portion is made from a dielectric material that has a lower dielectric constant than that of the upper portion.

Conclusion

Jun-bum Lee is an innovative inventor whose work in semiconductor memory devices showcases his potential in the field. His latest patent applications reflect a commitment to advancing technology in this area. As he continues to develop his ideas, it will be interesting to see how his contributions shape the future of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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