San Francisco, CA, United States of America

Julia Kroyan

This inventor holds 1 USPTO granted patent. Top assignee: Other. Active years: 2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Julia Kroyan. Retrieved from https://idiyas.com/inventor/julia-kroyan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 18(Granted Patents)


Company Filing History:

goldMedal1 out of 834,659 
Other
 patents

Years Active: 2009

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1 patent (USPTO):Explore Patents

Title: Julia Kroyan: Innovator in Layout Printability Optimization

Introduction

Julia Kroyan is a notable inventor based in San Francisco, CA. She has made significant contributions to the field of integrated circuits through her innovative work. Her expertise lies in enhancing manufacturability and yield, which is crucial for the advancement of technology.

Latest Patents

Julia holds 1 patent for her invention titled "Layout Printability Optimization Method and System." This patent presents a method that enhances the manufacturability and yield of integrated circuits. The method utilizes a mathematical framework to address layout printability problems through nonlinear numerical optimization techniques. It includes defining optimization objectives, constraint functions, computing function derivatives, and solving the resulting system.

Career Highlights

Throughout her career, Julia has demonstrated a strong commitment to innovation in the field of electronics. Her work has been instrumental in improving the efficiency of integrated circuit manufacturing processes. She continues to explore new methodologies that can further enhance the industry.

Collaborations

Julia collaborates with her coworker, Armen Kroyan, to advance their research and development efforts. Their partnership has led to significant advancements in their respective fields.

Conclusion

Julia Kroyan is a pioneering inventor whose work in layout printability optimization is shaping the future of integrated circuits. Her contributions are vital for the ongoing evolution of technology in this area.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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