Albuquerque, NM, United States of America

Josephine Sheng

This inventor holds 1 USPTO granted patent. Top assignee: The University of New Mexico. Active years: 2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Josephine Sheng. Retrieved from https://idiyas.com/inventor/josephine-sheng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2012

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1 patent (USPTO):Explore Patents

Title: Josephine Sheng and Semiconductor Surface Planarization

Introduction

Josephine Sheng is an inventor associated with Albuquerque, New Mexico, and The University of New Mexico. Her patent work addresses semiconductor manufacturing, particularly methods for preparing engineered germanium-on-silicon wafers.

Latest Patents

Sheng is credited with 1 patent: “Slurry-free chemical mechanical planarization (CMP) of engineered germanium-on-silicon wafers.” The invention describes planarizing a semiconductor surface using a slurry-free solution containing hydrogen peroxide and no abrasive particles, such as oxide particles. The process is intended to achieve a desirable surface roughness and can support the formation of high-quality Group III-V materials on the planarized surface.

Career Highlights

The patent reflects Sheng’s contribution to semiconductor processing research through a method designed to planarize materials such as germanium without conventional particle-based slurry. The disclosed approach focuses on surface quality and the preparation of semiconductor substrates for subsequent material growth.

Collaborations

Sheng’s listed coworkers include Sang M. Han and Darin Leonhardt. Her work is associated with The University of New Mexico.

Conclusion

Josephine Sheng’s patent highlights a slurry-free approach to semiconductor planarization that may help prepare engineered wafers for advanced materials and device research.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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