Joseph Sinohin Panganiban

Title: Joseph Sinohin Panganiban and Output-Capacitor-Stable Amplifier Design

Introduction

Joseph Sinohin Panganiban is an inventor associated with Lowell, Massachusetts, and Linear Technology Corporation. His patent work addresses stability in amplifier and buffer circuits used in applications such as linear voltage regulators.

Latest Patents

Panganiban is credited with 1 patent: “Compensation Technique Providing Stability Over Broad Range of Output Capacitor Values.” The invention describes an amplifier and buffer circuit with an input gain stage, an integrator, and a unity-gain output stage. Its compensation scheme maintains stable operation across a broad range of output capacitance.

With low to moderate output capacitance, the output-stage design pushes the output pole to higher frequencies, allowing the integrator’s internal pole to dominate and roll off gain at lower frequencies. With high output capacitance, the buffer’s input impedance couples the internal and output poles, making the output pole dominant while shifting the internal pole to higher frequencies. The connection can use a bipolar transistor’s base-emitter resistance or an MOS transistor with a separate resistor-capacitor circuit.

Career Highlights

Panganiban’s listed patent reflects work on circuit compensation and stability, particularly the challenge of maintaining reliable amplifier behavior as output-capacitor values vary. The supplied information associates him with Linear Technology Corporation.

Collaborations

Panganiban’s listed coworker is William Louis Walter. The available information identifies their association but does not specify the nature of their collaboration.

Conclusion

Joseph Sinohin Panganiban’s patent presents a compensation approach designed to preserve amplifier stability across a wide range of output-capacitor values.