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For the Inventor, By the Inventor

Hopkinton, MA, United States of America

Joseph M Lamb

This inventor holds 6 USPTO granted patents. Top assignee: Netronome Systems Incorporated. Active years: 2015-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Joseph M Lamb. Retrieved from https://idiyas.com/inventor/joseph-m-lamb-6k5qh1n8

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 6

% Patents Active = 83.3

Average Co-Inventor Count = 1.2

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:

goldMedal6 out of 175 
 
Netronome Systems Incorporated
 patents

Years Active: 2015-2018

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6 patents (USPTO):Explore Patents
1. 9891985 - 256-bit parallel parser and checksum circuit with 1-hot state information bus (2018-02-13),
2. 9515946 - High-speed dequeuing of buffer IDS in frame storing system (2016-12-06),
3. 9270488 - Reordering PCP flows as they are assigned to virtual channels (2016-02-23),
4. 9264256 - Merging PCP flows as they are assigned to a single virtual channel (2016-02-16),
5. 9258256 - Inverse PCP flow remapping for PFC pause frame generation (2016-02-09),
6. 9208844 - DDR retiming circuit (2015-12-08),

Title: Joseph M. Lamb: Innovator in High-Speed Data Processing

Introduction

Joseph M. Lamb is a notable inventor based in Hopkinton, MA (US). He has made significant contributions to the field of data processing, holding a total of six patents. His work focuses on enhancing the efficiency and speed of data handling systems.

Latest Patents

One of his latest patents is the "256-bit parallel parser and checksum circuit with 1-hot state information bus." This invention includes a 256-bit data bus and various state signal buses for IPV4, IPV6, TCP, and UDP protocols. The design allows for high-speed processing of packet data by utilizing multiple 64-bit parsing circuits that operate in parallel. Another significant patent is the "High-speed dequeuing of buffer IDs in frame storing system." This innovation involves a dual linked list of buffers maintained by a link manager, enabling efficient data retrieval at a rate exceeding the read access latency of pipelined memory.

Career Highlights

Joseph M. Lamb is currently employed at Netronome Systems Incorporated, where he continues to develop cutting-edge technologies in data processing. His work has been instrumental in advancing the capabilities of network processing systems.

Collaborations

Throughout his career, Joseph has collaborated with talented individuals such as Chunli Cai and Ranjit D. Loboprabhu. These partnerships have contributed to the successful development of innovative solutions in the field.

Conclusion

Joseph M. Lamb's contributions to data processing technology through his patents and collaborations highlight his role as a leading inventor in the industry. His work continues to influence advancements in high-speed data handling systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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