Berlin, Germany

Jorg Gwiasda

This inventor holds 3 USPTO granted patents. Top assignee: Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.v.. Active years: 1998-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jorg Gwiasda. Retrieved from https://idiyas.com/inventor/jorg-gwiasda

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.3

ph-index = 2

Forward Citations = 14(Granted Patents)


Company Filing History:


Years Active: 1998-1999

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3 patents (USPTO):Explore Patents

Title: Jorg Gwiasda: Innovator in Chip Technology

Introduction

Jorg Gwiasda is a prominent inventor based in Berlin, Germany. He has made significant contributions to the field of chip technology, holding a total of 3 patents. His work focuses on innovative solutions that enhance the manufacturing and functionality of chips.

Latest Patents

Among his latest patents are notable inventions such as a chip support arrangement and chip support for the manufacture of a chip. Additionally, he has developed a method for flip chip bonding using non-conductive adhesive. These patents reflect his commitment to advancing technology in the semiconductor industry.

Career Highlights

Jorg Gwiasda is affiliated with the Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung E.V., a leading research organization in Germany. His role at this esteemed institution allows him to collaborate with other experts and contribute to cutting-edge research in chip technology.

Collaborations

Throughout his career, Jorg has worked alongside talented colleagues, including Elke Zakel and Rolf Aschenbrenner. These collaborations have further enriched his research and innovation efforts.

Conclusion

Jorg Gwiasda's contributions to chip technology through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence advancements in semiconductor manufacturing and design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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