Chicago, IL, United States of America

Jonathan M Baker

This inventor holds 1 USPTO granted patent. Top assignee: The University of Chicago. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jonathan M Baker. Retrieved from https://idiyas.com/inventor/jonathan-m-baker-hqglzoc6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jonathan M. Baker and Quantum Error Correction

Introduction

Jonathan M. Baker is an inventor based in Chicago, Illinois, associated with the University of Chicago. His patent work addresses quantum computing, particularly the challenge of identifying and correcting errors in quantum systems.

Latest Patents

Baker is named on 1 patent: “System and Method of Decoding for Quantum Error Correction in Quantum Computing.” The invention describes a quantum computing system with logical qubits, classical memory, an on-chip decoder controller, and classical processing resources. During each cycle, the controller measures parity ancilla qubits and uses those measurements to generate error signatures for physical data qubits. It classifies the signatures as simple or complex, applies corrections for simple errors on-chip, and transfers complex signatures to a classical processor for off-chip decoding. This division of work is designed to support error correction within a quantum computing system.

Career Highlights

Baker’s listed patent reflects work at the intersection of quantum computing and error-correction methods. The disclosed approach combines on-chip processing with classical computation to handle different categories of error signatures.

Collaborations

The patent information lists Frederic T. Chong and Gokul Subramanian Ravi among Baker’s coworkers. Baker is associated with the University of Chicago.

Conclusion

Jonathan M. Baker’s patent focuses on a hybrid approach to quantum error correction, assigning simpler corrections to an on-chip controller and more complex decoding to classical processors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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