Burnaby, Canada

John Philip Plasterer

This inventor holds 5 USPTO granted patents. Top assignee: Pmc-Sierra, Inc.. Active years: 2004-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John Philip Plasterer. Retrieved from https://idiyas.com/inventor/john-philip-plasterer

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 80.0

Average Co-Inventor Count = 3.3

ph-index = 5

Forward Citations = 111(Granted Patents)


Company Filing History:


Years Active: 2004-2008

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5 patents (USPTO):Explore Patents

Title: Innovations of John Philip Plasterer

Introduction

John Philip Plasterer is a notable inventor based in Burnaby, Canada. He has made significant contributions to the field of technology, particularly in the development of advanced electronic systems. With a total of 5 patents to his name, Plasterer has demonstrated a commitment to innovation and excellence in his work.

Latest Patents

One of his latest patents is for an "In-phase and quadrature decision feedback equalizer." This invention provides an apparatus and method for equalizing a dispersive channel based on in-phase and quadrature samples corresponding to an input signal. The equalizer utilizes a novel adaptation algorithm to adjust filtering characteristics based on previous in-phase samples and a current quadrature sample. This adaptation algorithm updates filter coefficients in response to detecting a transition in the in-phase samples, effectively addressing quadrature post-cursor intersymbol interference (ISI) components of the input signal. Additionally, the equalizer can also equalize in-phase post-cursor ISI components, quadrature precursor ISI components, in-phase precursor ISI components, or a combination of these.

Another significant patent is for "Systems and methods for actively-peaked current-mode logic." This invention describes a method and apparatus for creating high-speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads. The logic cells can include buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads provide benefits such as reduced power consumption, smaller area, and higher speed performance compared to conventional devices. This performance enhancement is achieved using NMOS followers with resistively degenerated gates to create a frequency peaked transfer function of current-mode logic cells.

Career Highlights

John Philip Plasterer is currently employed at Pmc-Sierra, Inc., where he continues to innovate and develop cutting-edge technologies. His work has had a significant impact on the industry, particularly in the areas of signal processing and logic circuit design.

Collaborations

Throughout his career, Plasterer has collaborated with talented individuals such as Jurgen Hissen and Matthew W McAdam. These collaborations have contributed to the advancement of technology and the successful development of various projects.

Conclusion

John Philip Plasterer is a distinguished inventor whose work has greatly influenced the field of electronics

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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