San Jose, CA, United States of America

John E Readdie

This inventor holds 4 USPTO granted patents. Top assignees: Linear Technology Corporation, National Semiconductor Corporation. Active years: 1993-1994.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John E Readdie. Retrieved from https://idiyas.com/inventor/john-e-readdie

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 2

Forward Citations = 12(Granted Patents)


Company Filing History:


Years Active: 1993-1994

Loading Chart...
4 patents (USPTO):Explore Patents

Title: Innovations of John E Readdie

Introduction

John E Readdie is a notable inventor based in San Jose, CA (US). He holds a total of 4 patents that showcase his contributions to the field of electronics and semiconductor technology. His work has significantly impacted the design and functionality of various electronic components.

Latest Patents

One of his latest patents is for a high breakdown lateral PNP transistor. This invention is designed for use in programmable logic arrays. The lateral PNP transistor features a layer of oxide positioned between a polysilicon layer and the base along the base width. This oxide layer prevents the diffusion of the N+ dopant from the polysilicon layer into the N- base region, ensuring that the base remains N-. As a result, the transistor exhibits improved breakdown voltage characteristics while maintaining the speed advantages of polysilicon contact layers. The manufacturing method for this lateral PNP transistor requires minimal deviation from existing processes used for similar transistors.

Another significant patent involves a fabrication process for Schottky barrier diodes on a single poly bipolar. This method includes a process step that places a layer of oxide between the substrate and the overlying polysilicon layer, which is ultimately etched away. The oxide layer allows for the use of an end point dry etch process, facilitating greater miniaturization of circuits compared to traditional wet etch processes. This innovative approach also prevents overetching of the silicon material, resulting in a more ideal metal silicide anode-to-substrate Schottky barrier. Additionally, the oxide layer addresses Schottky mask alignment issues and enhances diode performance by eliminating parasitic diodes.

Career Highlights

Throughout his career, John E Readdie has worked with prominent companies in the semiconductor industry, including Linear Technology Corporation and National Semiconductor Corporation. His experience in these organizations has contributed to his expertise and innovative capabilities in the field.

Collaborations

John has collaborated with notable professionals such as Benjamin H Kwan and Jeng Chang. Their collective efforts have further advanced the development of semiconductor technologies.

Conclusion

John E Readdie's contributions to the field of electronics through his patents and collaborations highlight his innovative spirit and technical expertise. His work continues to influence the design and functionality of electronic components, making a lasting impact on the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…