Austin, TX, United States of America

Joel M Keys

This inventor holds 2 USPTO granted patents. Top assignee: Freescale Semiconductor,inc.. Active years: 2011-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Joel M Keys. Retrieved from https://idiyas.com/inventor/joel-m-keys

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2011-2013

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2 patents (USPTO):Explore Patents

Title: Joel M. Keys and High-Efficiency Semiconductor Amplifier Design

Introduction

Joel M. Keys is an inventor associated with Austin, Texas, and Freescale Semiconductor, Inc. His patent work includes semiconductor amplifier designs intended to reduce parasitic capacitance and improve power-added efficiency.

Latest Patents

Keys is associated with the patent titled “High Efficiency Amplifier with Reduced Parasitic Capacitance.” The invention describes a semiconductor amplifier built on a substrate with one or more unit amplifying cells. Dielectric-filled trench isolation walls surround individual cells and groups of cells, while selected semiconductor regions between the walls remain electrically floating relative to the substrate. This arrangement is designed to reduce parasitic capacitance and improve the amplifier’s power-added efficiency.

The patent also addresses excessive leakage between buried-layer contacts on high-resistivity substrates. It describes adding a semiconductor layer with intermediate doping between the substrate and the buried-layer contacts to help avoid that leakage. The supplied information lists 2 patents for Keys.

Career Highlights

Keys’s listed company is Freescale Semiconductor, Inc. His patent work reflects a focus on semiconductor device structures and amplifier performance.

Collaborations

The supplied information identifies Evan F. Yu and Dragan Zupac as Keys’s coworkers. Their specific contributions to the cited patent are not provided.

Conclusion

Joel M. Keys’s documented invention combines trench isolation and semiconductor-layer design to address parasitic capacitance, amplifier efficiency, and leakage in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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