Suwon, South Korea

Jiwon Kang

This inventor holds 1 USPTO granted patent and 4 published patent applications. Top assignees: Samsung Electronics Ltd., Seoul National University. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jiwon Kang. Retrieved from https://idiyas.com/inventor/jiwon-kang-6g4ypzv5

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jiwon Kang - Innovator in Semiconductor Technology

Introduction

Jiwon Kang is an inventor based in Suwon-si, South Korea. He is known for his contributions to semiconductor technology, focusing on innovative designs and applications. Although he currently holds no granted patents, his work in the field is noteworthy.

Latest Patent Applications

Jiwon Kang has submitted several patent applications that showcase his expertise. One of his latest applications is for a semiconductor package with a blocking element formed on a surface of an insulating layer. This design includes a semiconductor chip, an insulating layer structure, and a plurality of redistribution layers that are electrically connected to the chip. Additionally, the application describes an encapsulant and connection conductors that enhance the functionality of the semiconductor package.

Another significant application is for semiconductor devices and a method of manufacturing the same. This application details a substrate with a gate structure, a source/drain layer, and a contact plug that includes a barrier pattern and conductive layers. The innovative design aims to improve the efficiency and performance of semiconductor devices.

Conclusion

Jiwon Kang is an emerging inventor in the semiconductor field, with promising patent applications that reflect his innovative approach to technology. His work has the potential to contribute significantly to advancements in semiconductor design and manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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