San Jose, CA, United States of America

Jinwoo Kim

This inventor holds 2 USPTO granted patents. Top assignee: Mips Technologies, Inc.. Active years: 2011-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jinwoo Kim. Retrieved from https://idiyas.com/inventor/jinwoo-kim-ygsqueua

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 50.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2011-2012

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2 patents (USPTO):Explore Patents

Title: Jinwoo Kim: Innovator in Cache Control Technologies

Introduction

Jinwoo Kim is a notable inventor based in San Jose, CA (US). He has made significant contributions to the field of cache control technologies, holding a total of 2 patents. His work focuses on enhancing the efficiency and functionality of level-two cache systems.

Latest Patents

Jinwoo Kim's latest patents include an innovative apparatus and method for controlling the exclusivity mode of a level-two cache. This method involves generating level-two cache exclusivity control information at a processor in response to an exclusivity mode indicator. The generated information is then utilized to configure the exclusivity mode of the level-two cache, thereby improving its operational efficiency.

Career Highlights

Jinwoo Kim is currently employed at Mips Technologies, Inc., where he continues to develop cutting-edge technologies in the realm of cache systems. His expertise and innovative approach have positioned him as a key player in his field.

Collaborations

Jinwoo collaborates with various professionals in his industry, including his coworker, Darren Miller Jones. Their combined efforts contribute to the advancement of technology at Mips Technologies, Inc.

Conclusion

Jinwoo Kim's contributions to cache control technologies exemplify his dedication to innovation and excellence. His patents reflect a commitment to improving system performance and efficiency in computing environments.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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