Santa Clara, CA, United States of America

Jing Pu

This inventor holds 1 USPTO granted patent. Top assignee: Google Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jing Pu. Retrieved from https://idiyas.com/inventor/jing-pu-cj8u5kv3

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jing Pu: Inventor in Machine Learning Hardware Acceleration.

Introduction

Jing Pu is an inventor based in Santa Clara, California, and is associated with Google Inc. His work includes a patent on compiling and executing machine-learning inferences across hardware accelerators.

Latest Patents

Pu’s listed patent, “Hierarchical Compiling and Execution in a Machine Learning Hardware Accelerator,” describes a system for compiling and running machine-learning inferences across an array of multicore computing devices. The devices may be application-specific integrated circuits (ASICs), and the array can be adjusted to suit the requirements of each inference. The disclosure also describes compile-time optimization and scheduling across devices with multiple processing cores and core types. In some implementations, users can choose how much time or effort to devote to optimization during compilation, balancing compilation time against execution efficiency. Pu is listed with 1 patent.

Career Highlights

Pu’s patent reflects work at the intersection of machine learning and specialized computing hardware. Its focus on adaptable device arrays and configurable compile-time optimization addresses ways to improve the efficiency of inference execution.

Collaborations

Pu is associated with Google Inc. and is identified as a coworker of Jack Liu. The available information does not specify their particular projects or working relationship.

Conclusion

Jing Pu’s listed invention concerns flexible, optimized execution of machine-learning inferences on multicore hardware accelerators, highlighting the role of compilation and scheduling in efficient computing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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