Fremont, CA, United States of America

Jiabi J Zhu

This inventor holds 1 USPTO granted patent. Top assignee: Silicon Valley Research, Inc.. Active years: 1998.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jiabi J Zhu. Retrieved from https://idiyas.com/inventor/jiabi-j-zhu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 57(Granted Patents)


Company Filing History:


Years Active: 1998

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1 patent (USPTO):Explore Patents

Title: The Innovative Contributions of Jiabi J Zhu

Introduction

Jiabi J Zhu is a notable inventor based in Fremont, California. He has made significant contributions to the field of integrated circuit design, particularly through his innovative patent that addresses layout efficiency.

Latest Patents

Jiabi J Zhu holds a patent for an integrated circuit layout. This invention enables the rapid production of a dense layout for integrated circuits, allowing for smaller die sizes than previously possible. The result is a desirable reduction in the size of the final packaged integrated circuit. His approach combines routing space estimation and adjustment with area-based detailed routing, effectively merging the advantages of both channel-based and area-based layout techniques while minimizing their disadvantages.

Career Highlights

Jiabi J Zhu is currently employed at Silicon Valley Research, Inc. His work focuses on enhancing the efficiency and effectiveness of integrated circuit designs, contributing to advancements in the technology sector.

Collaborations

Jiabi collaborates with Cheng-Liang Ding, furthering the development of innovative solutions in integrated circuit technology.

Conclusion

Jiabi J Zhu's contributions to integrated circuit design exemplify the impact of innovation in technology. His work not only advances the field but also sets a foundation for future developments in integrated circuit efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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