Jeffrey Sather

Title: Jeffrey Sather: Patent Inventor in Capacitance Measurement

Introduction

Jeffrey Sather is an inventor associated with Plymouth, Minnesota, and LSI Logic Corporation. His patent work includes a method and system designed to measure capacitance while reducing the silicon area needed for probe pads.

Latest Patents

Sather is credited with 1 patent: “Method and System for Area Efficient Charge-Based Capacitance Measurement.” The invention uses multiple test structures connected to a target test capacitance structure, a reference structure, and a logic block. The logic block selects a suitable test structure, while a shared output pin buses test outputs. The design can also use multiple structure blocks and an additional logic block to select among them. By reducing the number of pins and probe pads required, the system aims to minimize silicon area.

Career Highlights

Sather’s listed patent reflects work on efficient semiconductor testing and measurement. The invention addresses the practical challenge of measuring capacitance while conserving space on a silicon device.

Collaborations

Sather’s listed coworker is Randall E. Bach. The patent information also associates his work with LSI Logic Corporation.

Conclusion

Jeffrey Sather’s patent describes an area-efficient approach to charge-based capacitance measurement, emphasizing reduced probe-pad requirements and streamlined test connections.