This inventor holds 1 USPTO granted patent. Top assignee: Motorola Corporation. Active years: 1999.
Company Filing History:
Years Active: 1999
Title: The Innovations of Jeffrey R. Hardesty
Introduction
Jeffrey R. Hardesty is a notable inventor based in Austin, TX, who has made significant contributions to the field of processor technology. His innovative work has led to the development of a unique method for clock generation in processors, enhancing their performance and reliability.
Latest Patents
One of Hardesty's key patents is titled "Fast start-up processor clock generation method and system." This invention introduces a phase-locked loop (PLL) based clock generation circuit that allows for processor execution during the phase locking process. The PLL generates a clock output that is divided to create a system clock output. This system enables the CPU to execute tasks at a divided frequency while safely achieving phase lock, thus preventing frequency overshoot failures.
Career Highlights
Jeffrey R. Hardesty has had a distinguished career at Motorola Corporation, where he has applied his expertise in electronics and processor design. His innovative approach to clock generation has positioned him as a valuable asset in the field of technology.
Collaborations
Throughout his career, Hardesty has collaborated with talented individuals such as Geoffrey B. Hall and Kelvin E. McCollough. These partnerships have contributed to the advancement of technology and the successful development of innovative solutions.
Conclusion
Jeffrey R. Hardesty's contributions to processor technology through his patent on clock generation methods exemplify his innovative spirit and dedication to enhancing electronic performance. His work continues to influence the field and inspire future advancements.