Aix-en-Provence, France

Jean-Max Dutertre

This inventor holds 1 USPTO granted patent. Top assignee: Institut Mines-Telecom. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jean-Max Dutertre. Retrieved from https://idiyas.com/inventor/jean-max-dutertre-srsc3e7z

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Innovations of Jean-Max Dutertre

Introduction

Jean-Max Dutertre is a notable inventor based in Aix-en-Provence, France. He has made significant contributions to the field of electronic memory through his innovative methods. His work focuses on enhancing the reliability of non-volatile semiconductor memories.

Latest Patents

Jean-Max Dutertre holds a patent for a "Method for detecting an error in an electronic memory." This method addresses the detection of faults caused by photoelectric or radiative effects in non-volatile semiconductor memory. The memory includes a plurality of memory cells containing MOS transistors, potentially floating-gate MOS transistors. Each memory cell is strategically located at the intersection of an elementary bit line and a word line. This innovation is crucial for improving the performance and reliability of electronic devices.

Career Highlights

Dutertre is associated with the Institut Mines-Telecom, where he continues to contribute to advancements in technology. His expertise in electronic memory systems has positioned him as a valuable asset in the field of semiconductor research.

Collaborations

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Conclusion

Jean-Max Dutertre's work exemplifies the importance of innovation in electronic memory technology. His patent reflects a commitment to enhancing the reliability of semiconductor devices. His contributions are vital for the ongoing development of advanced electronic systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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