Heverlee, Belgium

Javier Diaz Fortuny

This inventor holds 1 USPTO granted patent and 1 EPO patent. Top assignees: Imec Vzw, Katholieke Universiteit Leuven, K.u.leuven R&D. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Javier Diaz Fortuny. Retrieved from https://idiyas.com/inventor/javier-diaz-fortuny

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0


Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Javier Diaz Fortuny and Tamper-Aware Age Sensing

Introduction

Javier Diaz Fortuny is an inventor based in Heverlee, Belgium. His patent work includes a sensor designed to estimate the operating age of an integrated circuit by monitoring performance degradation.

Latest Patents

The provided information lists one patent associated with Fortuny: “Tamper-aware age sensor.” The invention describes a sensor that can operate in regular-use or readout mode. It combines a performance monitor responsive to temperature and voltage stress with a pre-stressed anneal monitor responsive to temperature stress. In regular-use mode, the performance monitor receives the integrated circuit’s operating voltage. In readout mode, both monitor types generate output signals indicating performance degradation. The patent also describes a related tamper-detection method.

Career Highlights

Fortuny’s listed professional affiliations include Katholieke Universiteit Leuven, K.U. Leuven R&D, and imec vzw. His work on age sensing addresses the challenge of assessing integrated-circuit degradation and detecting potential tampering.

Collaborations

His listed coworkers include Robin Degraeve and Benjamin Kaczer.

Conclusion

Javier Diaz Fortuny’s patent on tamper-aware age sensing brings together stress monitoring and degradation assessment to help evaluate the operating age and integrity of integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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