Jason R Potnick

Title: Jason R Potnick: Innovator in Integrated Circuit Timing Design

Introduction

Jason R Potnick is a notable inventor based in Livermore, CA (US). He has made significant contributions to the field of integrated circuit design, particularly in timing analysis. His innovative approach has led to the development of a unique method that enhances the accuracy of timing margins in circuit designs.

Latest Patents

Jason holds a patent for a method titled "Frequency dependent timing margin." This invention focuses on determining a timing margin to be applied in an integrated circuit timing design. The process involves analyzing circuit simulator path delays and static timing analysis tool path delays. By plotting these delays and identifying key points, Jason's method effectively combines both the circuit simulator path delay and the percentage difference to establish a reliable timing margin. He has 1 patent to his name.

Career Highlights

Jason is currently employed at LSI Corporation, where he applies his expertise in integrated circuit design. His work has been instrumental in advancing the company's capabilities in timing analysis and circuit design. His innovative contributions have positioned him as a valuable asset in the field.

Collaborations

Throughout his career, Jason has collaborated with talented individuals such as Qian Cui and Sandeep Bhutani. These partnerships have fostered a creative environment that encourages innovation and the sharing of ideas.

Conclusion

Jason R Potnick is a distinguished inventor whose work in integrated circuit timing design has made a significant impact. His patent on frequency dependent timing margins showcases his innovative thinking and dedication to improving circuit design accuracy. His contributions continue to influence the field and inspire future advancements.