Fontainebleau, France

Jan Keller

This inventor holds 1 USPTO granted patent. Top assignees: Altis Semiconductor, Snc, Qimonda Ag. Active years: 2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jan Keller. Retrieved from https://idiyas.com/inventor/jan-keller-3m3wwn1r

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2010

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1 patent (USPTO):Explore Patents

Title: Jan Keller: Innovator in Integrated Circuit Technology

Introduction

Jan Keller is a notable inventor based in Fontainebleau, France. He has made significant contributions to the field of integrated circuits, particularly in memory devices. His innovative work has led to the development of a patent that enhances the functionality of memory modules.

Latest Patents

Jan Keller holds a patent for an integrated circuit that includes a method of reading data stored within a memory device, a method of writing data into a memory device, and a memory module. The patent describes a memory device comprising a plurality of memory cells, each consisting of a first electrode, a second electrode, and an active material arranged between them. The memory cells are organized into groups, allowing for individual addressing of first electrodes and common addressing of second electrodes through a select device.

Career Highlights

Throughout his career, Jan Keller has worked with prominent companies in the semiconductor industry. He has been associated with Qimonda AG and Altis Semiconductor, SNC, where he contributed to advancements in memory technology and integrated circuits.

Collaborations

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Conclusion

Jan Keller's contributions to integrated circuit technology and memory devices highlight his role as an innovator in the field. His patent reflects a significant advancement that could influence future developments in memory technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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