Zubri, Czechia

Jan Hybl

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Semiconductor Components Industries, LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jan Hybl. Retrieved from https://idiyas.com/inventor/jan-hybl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jan Hybl and Semiconductor Manufacturing Innovation.

Introduction

Jan Hybl is an inventor associated with Zubří, Czech Republic, and semiconductor technology. His patent work addresses methods for manufacturing semiconductor devices and improving the properties of CZ silicon substrates.

Latest Patents

Hybl is credited with 1 patent: “Methods of Manufacturing Semiconductor Devices and Semiconductor Devices.” The disclosed method uses two annealing steps: first, an unpolished CZ silicon substrate is annealed in an inert environment; then it is annealed in a wet oxidation environment. The first step dissolves inner-wall oxide in voids within the substrate, while the second helps fill those voids with semiconductor interstitials. The patent describes potential benefits including fewer crystal-originated particle defects, lower oxygen concentration, and reduced radial resistivity variation. Some examples use CZ silicon grown in a magnetic field with continuous counter-doping.

Career Highlights

Hybl’s listed company is Semiconductor Components Industries, LLC. The patent reflects work focused on silicon substrate processing and semiconductor-device manufacturing.

Collaborations

David Lysacek and Dusan Postulka are identified as Hybl’s coworkers. The provided information does not specify their roles in the patent or the extent of their collaboration.

Conclusion

Jan Hybl’s patent centers on annealing techniques intended to improve CZ silicon substrates and support semiconductor manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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