James M Garnett

Title: James M Garnett: Innovator in Memory Testing Algorithms

Introduction

James M Garnett is a notable inventor based in Wilsonville, OR (US). He has made significant contributions to the field of memory testing algorithms, particularly through his innovative patent. His work is recognized for enhancing the reliability of memory arrays in electronic devices.

Latest Patents

James M Garnett holds a patent for a "Short Disturb Test Algorithm for Built-In Self-Test." This algorithm is designed to improve the testing process of memory arrays. The method involves initially writing a background pattern to all cells in a memory array. After verifying that the background pattern was written, the opposite of the background pattern is written to a single row of the memory array for a fixed time. Once this time elapses, the original background pattern is restored to the row. The memory array is then refreshed, and the next row is processed. After all rows have been written to, the memory array is checked for failures. This innovative approach enhances the efficiency and accuracy of memory testing.

Career Highlights

James M Garnett is currently employed at Texas Instruments Corporation, where he continues to develop and refine technologies related to memory testing. His expertise in this area has made him a valuable asset to the company and the industry as a whole.

Collaborations

Throughout his career, James has collaborated with talented individuals such as Siak Kian Lee and Danny R Cline. These collaborations have contributed to the advancement of technology in the field of memory testing.

Conclusion

James M Garnett is a distinguished inventor whose work in memory testing algorithms has made a significant impact on the industry. His innovative patent demonstrates his commitment to enhancing technology and improving the reliability of electronic devices.