Irvine, CA, United States of America

Jaifu Luo

This inventor holds 1 USPTO granted patent. Top assignee: Ess Technology, Inc.. Active years: 2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaifu Luo. Retrieved from https://idiyas.com/inventor/jaifu-luo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2007

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1 patent (USPTO):Explore Patents

Title: Jaifu Luo and His Multi-Stage Amplifier Patent.

Introduction

Jaifu Luo is an inventor associated with Irvine, California, and Ess Technology, Inc. His patent work includes an amplifier design that uses switching circuitry to support multiple stages with a shared operational amplifier.

Latest Patents

The provided information lists one patent for Jaifu Luo: 1 patent. The patent, “Multi-stage amplifier with switching circuitry,” describes an amplifier circuit, a method of operating it, and a device incorporating it. The design shares an operational amplifier among multiple stages, while switching circuitry selects different input signals and feedback paths for each stage. The circuitry can also store and discharge charge at one or more operational-amplifier inputs.

Career Highlights

Luo’s listed invention focuses on circuit architecture and amplifier operation. By reusing an operational amplifier across stages and switching its inputs and feedback, the design addresses how a multi-stage amplifier can operate with shared components.

Collaborations

The provided information identifies Mehmet Ali Tan and Rajagopal Sundararaman as Luo’s coworkers. Their names are associated with his professional context, though no specific joint patent or project is specified.

Conclusion

Jaifu Luo’s listed patent presents a multi-stage amplifier approach built around a shared operational amplifier and switching circuitry, reflecting his work in electronic circuit design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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