Jagdish M Sbade

Title: Innovations by Jagdish M Sbade in Non-Volatile Memory Technology

Introduction

Jagdish M Sbade is an accomplished inventor based in Fremont, CA, known for his contributions to the field of non-volatile memory technology. With a focus on improving memory array performance, he has developed innovative techniques that address critical issues in memory design.

Latest Patents

One of his notable patents is titled "Determination of bit line to low voltage signal shorts." This patent presents a number of techniques for identifying defects in non-volatile memory arrays, particularly applicable to 3D NAND memory, such as that of the BiCS type. The invention outlines methods for determining word line to word shorts within a memory block through the application of an AC stress mode, followed by a defect detection operation. Additionally, it describes an inter-block stress and detection operation to identify word line to word line leaks between different blocks. The patent also considers select gate leakage, both from word lines and other select lines, as well as shorts from word lines and select lines to local source lines. Furthermore, it introduces techniques for determining shorts between bit lines and low voltage circuitry, such as in sense amplifiers.

Career Highlights

Jagdish M Sbade has made significant strides in his career, particularly through his work at SanDisk Technologies Inc. His expertise in memory technology has positioned him as a key player in the development of advanced memory solutions.

Collaborations

He has collaborated with various professionals in the field, including his coworker Sagar Magia, to further enhance the innovation landscape in memory technology.

Conclusion

Jagdish M Sbade's contributions to non-volatile memory technology exemplify the importance of innovation in addressing complex challenges in the field. His patent on detecting shorts in memory arrays showcases his commitment to advancing technology and improving memory performance.