Jagadeesh Vasudevamurthy

Title: Innovations by Jagadeesh Vasudevamurthy

Introduction

Jagadeesh Vasudevamurthy is an accomplished inventor based in San Jose, CA. He has made significant contributions to the field of integrated circuit design, holding 2 patents that showcase his expertise in optimizing hardware designs.

Latest Patents

One of his latest patents is titled "Prediction of Logic Optimization Algorithms Using Machine Learning." This patent focuses on combinational logic circuit optimization. The techniques described in this patent aim to enhance hardware design for integrated circuits. Instead of employing multiple optimization strategies each time design code is synthesized, the invention identifies the optimal strategy for a specific combinational module in the design code. This approach allows the synthesis tool to recognize the module and select the best optimization strategy for future syntheses. The synthesis tool generates a signature based on the circuit structure represented by a netlist, traversing the netlist to assign unique integers to primary inputs, combination instances, and primary outputs. These integers are then processed by a signature generator to produce a signature for the combinational module.

Career Highlights

Jagadeesh currently works at Xilinx, Inc., a leading company in the field of programmable logic devices. His work at Xilinx has allowed him to apply his innovative ideas and contribute to advancements in integrated circuit technology.

Collaborations

He collaborates with talented coworkers, including Akhil Tharad and Aman Gayasen, who share his passion for innovation and technology.

Conclusion

Jagadeesh Vasudevamurthy's contributions to the field of integrated circuit design through his patents and work at Xilinx, Inc. highlight his role as a significant innovator in the industry. His focus on optimizing hardware design through machine learning techniques sets a precedent for future advancements in the field.