Bucheon, South Korea

Jaein An

This inventor holds 1 USPTO granted patent. Top assignee: Semiconductor Components Industries, LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaein An. Retrieved from https://idiyas.com/inventor/jaein-an

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jaein An and His Semiconductor Patent

Introduction

Jaein An is an inventor associated with Bucheon, South Korea. His patent work concerns semiconductor device design, particularly electrical connections among transistor gates and source regions. He is associated with Semiconductor Components Industries, LLC.

Latest Patents

The provided information lists one patent for Jaein An: “Transistors with Selectively Landed Gate Array.” The patent describes a semiconductor device containing multiple transistors and arrays of low-resistance material formed in dielectric layers. One array connects to the transistors’ gate electrodes and source regions, while a second array lands on corresponding portions of the first array to establish electrical connections. This arrangement addresses how conductive material can be selectively positioned to connect transistor components.

Career Highlights

An’s listed patent reflects work in semiconductor components and transistor interconnect structures. The supplied information identifies 1 patent associated with him and names Semiconductor Components Industries, LLC as his company.

Collaborations

The provided information names Jimmy Robert Hannes Franchi and Krister Gumaelius as An’s coworkers. Their specific roles or contributions to the patent are not stated.

Conclusion

Jaein An’s listed invention focuses on selectively landed conductive arrays that connect transistor gates and source regions, highlighting his contribution to semiconductor device design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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