Suwon, South Korea

Jae Won Na

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jae Won Na. Retrieved from https://idiyas.com/inventor/jae-won-na-mikmj5x6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jae Won Na and Semiconductor Memory Device Innovation.

Introduction

Jae Won Na is an inventor based in Suwon, South Korea. His patent work includes semiconductor memory technology, and he is associated with Samsung Electronics Ltd.

Latest Patents

Na is credited with 1 patent, titled “Semiconductor Memory Device.” The invention describes a device with bit lines on a substrate, active pillars positioned on the bit lines, and a word line that extends along the pillars in a wavy shape when viewed from above. Landing pads and data storage patterns are positioned above the active pillars, forming part of the memory structure.

Career Highlights

Na’s listed patent reflects work on the structure and arrangement of components in semiconductor memory devices. His company affiliation connects this work with Samsung Electronics Ltd.

Collaborations

Na’s listed coworkers include Junhwa Song and Dong-sik Park.

Conclusion

Jae Won Na’s patent focuses on a semiconductor memory device architecture featuring active pillars and a wavy word line, highlighting his contribution to memory technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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