Suwon, South Korea

J O-won Lee

This inventor holds 1 USPTO granted patent. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: J O-won Lee. Retrieved from https://idiyas.com/inventor/j-o-won-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 72(Granted Patents)


Company Filing History:


Years Active: 2005

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1 patent (USPTO):Explore Patents

Title: J O-won Lee and Semiconductor Etch-Stopper Innovation.

Introduction

J O-won Lee is an inventor associated with Suwon, South Korea, and Samsung Electronics Co., Ltd. His patent work includes a semiconductor fabrication approach designed to protect the substrate during etching.

Latest Patents

Lee is credited with 1 patent: “Semiconductor Device Having an Etch Stopper Formed of a SiN Layer by Low Temperature ALD and Method of Fabricating the Same.” The invention describes forming a first nitride film on a semiconductor substrate using high-temperature low-pressure chemical vapor deposition, then depositing a second nitride film as an etch stopper using low-temperature atomic layer deposition. Dry etching removes the second film while taking advantage of the films’ different etch selectivities, helping prevent damage to the substrate beneath the etch stopper.

Career Highlights

Lee’s listed patent reflects work on semiconductor manufacturing processes, particularly thin-film deposition and etch control. The approach combines high-temperature LPCVD with low-temperature ALD to improve substrate protection during fabrication.

Collaborations

The provided information lists Jong-Ho Yang and Kang-soo Chu as Lee’s coworkers. Their names are associated with his professional context, though specific roles in the patent are not stated.

Conclusion

J O-won Lee’s patent describes a layered nitride-film process that uses differing etch selectivities to protect semiconductor substrates during fabrication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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