J J Grady, Iii

Title: J J Grady, III: Innovator in Cache Invalidation Mechanisms

Introduction

J J Grady, III is a notable inventor based in Woburn, MA (US). He has made significant contributions to the field of multiprocessor systems, particularly in cache invalidation mechanisms. His innovative work has led to the development of a patent that addresses critical issues in data management within multiprocessor environments.

Latest Patents

Grady holds a patent for a "Cache invalidation mechanism for multiprocessor systems." This invention involves a system where one of several devices on a common communications path has a local memory accessible by other devices. The patent outlines how a cache memory can maintain copies of data from the local memory and how it can be kept updated through monitoring the communications path. This mechanism allows for efficient data access while ensuring that cache memories are properly invalidated when necessary.

Career Highlights

J J Grady, III has worked at Digital Equipment Corporation, where he has been able to apply his expertise in computer systems and memory management. His work has been instrumental in enhancing the performance and reliability of multiprocessor systems.

Collaborations

Grady has collaborated with notable colleagues such as Frank C Bomba and Dileep P Bhandarkar. These collaborations have contributed to the advancement of technology in their respective fields.

Conclusion

J J Grady, III is a distinguished inventor whose work in cache invalidation mechanisms has made a significant impact on multiprocessor systems. His innovative solutions continue to influence the field of computer science and engineering.