Migdal Haemek, Israel

Ishai Naveh

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Tower Semiconductor Ltd.. Active years: 2010-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ishai Naveh. Retrieved from https://idiyas.com/inventor/ishai-naveh-7dl4w3c5

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 2

Forward Citations = 41(Granted Patents)


Location History:

  • San-Jose, CA (US) (2010)
  • Migdal Haemek, IL (2011)

Company Filing History:


Years Active: 2010-2011

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2 patents (USPTO):Explore Patents

Title: Ishai Naveh: Inventor in Non-Volatile Memory Technology

Introduction

Ishai Naveh is an inventor based in Migdal Haemek, Israel. His work includes semiconductor memory technology, and he is associated with Tower Semiconductor Ltd. His listed portfolio includes 2 patents.

Latest Patents

Naveh’s latest listed patent is titled “Asymmetric Single Poly NMOS Non-Volatile Memory Cell.” It describes an asymmetric non-volatile memory cell for a CMOS integrated circuit made using a standard process flow that supports both low-voltage and high-voltage transistors.

The cell includes an NMOS floating-gate transistor and may include a select transistor. Its elongated floating gate extends from the channel region into an enlarged drain diffusion area, creating greater gate-to-drain capacitance than gate-to-source capacitance. The design also describes minimizing the width of the floating-gate extension and combining high-voltage and low-voltage LDD implants to enable implant merging beneath that extension. It further discusses replacing the high-voltage LDD implant in the memory transistor with a low-voltage LDD implant, using substantially U-shaped or J-shaped polysilicon structures, and implementing different array-addressing schemes.

Career Highlights

Naveh’s listed invention addresses the integration of non-volatile memory into CMOS processes, with design features intended to support memory-cell operation within a standard semiconductor manufacturing flow. His professional association with Tower Semiconductor Ltd. connects his work to the semiconductor industry.

Collaborations

Naveh’s listed coworkers include Evgeny Pikhay and Yakov Roizin.

Conclusion

Ishai Naveh’s patent work focuses on an asymmetric single-poly NMOS non-volatile memory cell and its integration into CMOS technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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