Austin, TX, United States of America

Irfan Waheed

This inventor holds 2 USPTO granted patents. Top assignee: Apple Inc.. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Irfan Waheed. Retrieved from https://idiyas.com/inventor/irfan-waheed

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2013

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2 patents (USPTO):Explore Patents

Title: Innovations of Irfan Waheed

Introduction

Irfan Waheed is a notable inventor based in Austin, TX (US). He has made significant contributions to the field of integrated circuit design and verification. With a total of 2 patents, his work focuses on enhancing the efficiency and accuracy of semiconductor design processes.

Latest Patents

Irfan Waheed's latest patents include a "Method for piecewise hierarchical sequential verification." This invention describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled. The semiconductor design is partitioned and associated input constraints. The edits are further grouped and ordered. The invention also discovers a set of dependencies of the logic edits and checks that the ordering of groups obeys the dependencies. Each group of edits is further submitted to formal verification, and any input constraints assumed for any partitions are verified in their enclosing partition. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints.

Another significant patent is the "Method for preparing for and formally verifying a modified integrated circuit design." This method prepares an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.

Career Highlights

Irfan Waheed is currently employed at Apple Inc., where he continues to innovate and contribute to the field of semiconductor design. His work is instrumental in advancing the technology used in integrated circuits.

Collaborations

Irfan has collaborated with

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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