This inventor holds 1 USPTO granted patent. Top assignee: Tower Semiconductor Ltd.. Active years: 2020.
Company Filing History:
Years Active: 2020
Title: Igor Aisenberg: Innovator in Semiconductor Technology
Introduction
Igor Aisenberg is a notable inventor based in Afula, Israel. He has made significant contributions to the field of semiconductor technology, particularly in enhancing the performance of NMOS transistors. His innovative approach has led to the development of a unique patent that addresses critical challenges in the industry.
Latest Patents
Igor Aisenberg holds a patent titled "Stressing structure with low hydrogen content layer over NiSi salicide." This invention involves a multi-layer SiN stressing stack that includes a thin lower SiN layer and a thick upper SiN layer formed over NiSi silicide structures. The design generates tensile channel stress in NMOS transistors, which is crucial for improving the mobility of channel electrons. The lower SiN layer, characterized by low hydrogen content and relatively low residual stress, acts as a barrier to prevent hydrogen migration to the silicide structures, thereby minimizing defects that could lead to NiSi failures. The upper SiN layer, on the other hand, is engineered to produce high residual stress and contains a higher hydrogen content, which contributes to the desired tensile stress in the NMOS channel region.
Career Highlights
Igor Aisenberg is currently associated with Tower Semiconductor Ltd., where he continues to push the boundaries of semiconductor innovation. His work has been instrumental in developing technologies that enhance the performance and reliability of semiconductor devices.
Collaborations
Igor has collaborated with notable colleagues, including Abed Qaddah and Yakov Roizin, who have contributed to his research and development efforts in the semiconductor field.
Conclusion
Igor Aisenberg's contributions to semiconductor technology, particularly through his innovative patent, highlight his role as a key inventor in the industry. His work not only addresses existing challenges but also paves the way for future advancements in NMOS transistor performance.