Taipei, Taiwan

Hung-chi Tsai

This inventor holds 2 USPTO granted patents and 4 published patent applications. Top assignee: Nan Ya Technology Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hung-chi Tsai. Retrieved from https://idiyas.com/inventor/hung-chi-tsai-uh5pvohl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Hung-chi Tsai and Semiconductor Device Innovation

Introduction

Hung-chi Tsai is an inventor associated with Taipei, Taiwan. His patent work includes a semiconductor device design and a method for fabricating it. The available information identifies Nan Ya Technology Corporation as his company.

Latest Patents

The listed patent, “Semiconductor Device and Method for Fabricating the Same,” describes a device built on a substrate with a gate structure and multiple word lines. Porous spacers sit on either side of the gate structure, while a first insulating layer surrounds the gate structure and spacers laterally. A second insulating layer lies above the first. The design specifies aligned top surfaces for the gate structure, word lines, and second insulating layer, and porous spacers with porosity of about 25% to 100%. Tsai is associated with 1 patent in the information provided.

Career Highlights

Tsai’s documented patent activity focuses on semiconductor device architecture and fabrication. His association with Nan Ya Technology Corporation connects his work to the company’s technology and innovation efforts.

Collaborations

The available information names Nan Ya Technology Corporation as Tsai’s company but does not identify specific co-inventors or other collaborators for the listed patent.

Conclusion

Hung-chi Tsai’s listed patent presents a semiconductor device design that combines porous spacers, insulating layers, and carefully aligned structures, reflecting his documented contribution to semiconductor innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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