Hsinchu, Taiwan

Horng-Jyh Liu

This inventor holds 1 USPTO granted patent. Top assignee: Silicon Integrated Systems Corporation. Active years: 2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Horng-Jyh Liu. Retrieved from https://idiyas.com/inventor/horng-jyh-liu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 22(Granted Patents)


Company Filing History:


Years Active: 2001

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1 patent (USPTO):Explore Patents

Title: Horng-Jyh Liu: Innovator in Flip-Flop Technology

Introduction: Horng-Jyh Liu is a prominent inventor based in Hsinchu, Taiwan. He is known for his innovative contributions to digital circuit design, particularly in the development of flip-flop technology. His work has significantly impacted the efficiency of data processing systems.

Latest Patents: Liu holds a patent for a "Double Edge Trigger D-Type Flip-Flop." This invention allows for triggering at both the rising and falling edges of a clock signal. As a result, the double edge trigger D-type flip-flop can access data twice within a single clock cycle. This capability effectively doubles the data access compared to conventional flip-flops, leading to enhanced system efficiency.

Career Highlights: Liu is currently employed at Silicon Integrated Systems Corporation, where he continues to innovate in the field of integrated circuits. His work has been instrumental in advancing the capabilities of digital systems.

Collaborations: Liu has collaborated with notable colleagues, including Hsing-Yi Chen and Stanley Liao. Their combined expertise has contributed to the success of various projects within their organization.

Conclusion: Horng-Jyh Liu's contributions to flip-flop technology exemplify the importance of innovation in enhancing system performance. His patent for the double edge trigger D-type flip-flop represents a significant advancement in digital circuit design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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