Hamburg, Germany

Holger Thiel

This inventor holds 1 USPTO granted patent. Top assignee: Koninklijke Philips Corporation N.v.. Active years: 2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Holger Thiel. Retrieved from https://idiyas.com/inventor/holger-thiel-vkalmtam

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2004

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1 patent (USPTO):Explore Patents

Title: Holger Thiel - Innovator in Circuit Arrangement Technology

Introduction

Holger Thiel is a notable inventor based in Hamburg, Germany. He has made significant contributions to the field of integrated circuit technology. His innovative work focuses on enhancing the efficiency and cost-effectiveness of testing integrated circuits.

Latest Patents

Holger Thiel holds a patent for a circuit arrangement designed for controlling a first terminal and a second terminal of a contactless integrated circuit. This invention is particularly useful for testing CMOS circuits. The circuit arrangement allows for the simultaneous testing of multiple integrated circuits while utilizing a low-cost structure. It also facilitates a simple write/read unit assigned to the integrated circuit, making the testing process more efficient.

Career Highlights

Holger Thiel is associated with Koninklijke Philips Corporation N.V., where he has contributed to various projects in the field of electronics and integrated circuits. His work has been instrumental in advancing technologies that are crucial for modern electronic devices.

Collaborations

Some of his notable coworkers include Michael Liebig and Wolfgang Tobergte. Their collaboration has further enhanced the innovative capabilities within their projects.

Conclusion

Holger Thiel's contributions to circuit arrangement technology exemplify the impact of innovation in the field of integrated circuits. His work continues to influence the efficiency of testing processes in electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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