Harihara Ganesan

Title: Harihara Ganesan: Inventor in Integrated-Circuit Verification

Introduction

Harihara Ganesan is an inventor based in San Jose, California. His patent work addresses ways to improve verification of integrated-circuit designs by generating simulation input for coverage goals that existing tests have not reached.

Latest Patents

Ganesan is associated with 1 patent: “Technique for Generating Input Stimulus to Cover Properties Not Covered in Random Simulation.” The invention begins with directed and/or random test cases used to verify an integrated-circuit design. When those tests do not cover a specified directive, the method creates a property whose failure can identify a simulation trace that covers it. The property is then evaluated, and, depending on the result, the trace is dumped and stored for later use in exercising the coverage directive.

Career Highlights

Ganesan’s listed patent is associated with Sun Microsystems, Inc. It reflects work on simulation-based verification and on using uncovered properties to guide the generation and reuse of test stimuli.

Collaborations

The provided information lists Yick Kei Wong and William K. Lam as Ganesan’s coworkers.

Conclusion

Harihara Ganesan’s patent describes a targeted approach to finding and preserving simulation traces that help cover verification goals missed by directed or random testing.