San Jose, CA, United States of America

Hari Devanath

This inventor holds 1 USPTO granted patent. Top assignee: Xilinx, Inc.. Active years: 2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hari Devanath. Retrieved from https://idiyas.com/inventor/hari-devanath

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2011

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1 patent (USPTO):Explore Patents

Title: Innovations of Hari Devanath

Introduction

Hari Devanath is an accomplished inventor based in San Jose, California. He has made significant contributions to the field of design-specific input/output modeling. His innovative approach has led to the development of a unique patent that enhances circuit design processes.

Latest Patents

Hari Devanath holds a patent for "Generating a design-specific input/output model document." This method involves reading multiple I/O pin models corresponding to available I/O pin profiles on a target device. It identifies the I/O pins used by a circuit design and determines the I/O pin profile for each pin. The process includes selecting an I/O pin model from the available options based on these profiles. Ultimately, a design-specific I/O model document is generated, which incorporates each selected I/O pin model.

Career Highlights

Hari is currently employed at Xilinx, Inc., where he continues to innovate and contribute to the field of electronic design automation. His work focuses on improving the efficiency and accuracy of circuit design through advanced modeling techniques.

Collaborations

Some of his notable coworkers include Paul Cheng and Jennifer D Baldwin, who collaborate with him on various projects at Xilinx, Inc.

Conclusion

Hari Devanath's contributions to the field of design-specific I/O modeling demonstrate his commitment to innovation and excellence. His patent reflects a significant advancement in circuit design methodologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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