Roedermark, Germany

Hans Isert

This inventor holds 1 USPTO granted patent. Top assignee: Telenorma Telefonbau Und Normalzeit Gmbh. Active years: 1991.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hans Isert. Retrieved from https://idiyas.com/inventor/hans-isert

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 20(Granted Patents)


Company Filing History:


Years Active: 1991

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1 patent (USPTO):Explore Patents

Title: The Innovations of Hans Isert

Introduction

Hans Isert is a notable inventor based in Rodermark, Germany. He has made significant contributions to the field of electrical components, particularly through his innovative designs in electronic modular units. His work has paved the way for advancements in integrated semiconductor technology.

Latest Patents

Hans Isert holds a patent for an electronic modular unit that can be bonded to a support or another modular unit. This inventive electronic unit features projections or recesses that allow for seamless mating between units. The projections can be formed through an etching process, enabling both electrical and mechanical connections between the units.

Career Highlights

Hans Isert is associated with Telenorma Telefonbau und Normalzeit GmbH, where he has contributed to various projects in the telecommunications sector. His expertise in electrical components has been instrumental in the development of advanced technologies within the company.

Collaborations

Hans has worked alongside his coworker Wolfgang Schafer, collaborating on various projects that leverage their combined expertise in electrical engineering and modular design.

Conclusion

Hans Isert's innovative work in electronic modular units exemplifies the impact of creativity and engineering in advancing technology. His contributions continue to influence the field of electrical components and semiconductor design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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