Tustin, CA, United States of America

Hamza Khan

This inventor holds 1 USPTO granted patent. Top assignee: Xcelerium Inc. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hamza Khan. Retrieved from https://idiyas.com/inventor/hamza-khan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Hamza Khan and Variable-Precision Matrix Multiplication

Introduction

Hamza Khan is an inventor based in Tustin, California. His patent work addresses efficient matrix multiplication, a computational operation used in areas such as artificial intelligence and digital signal processing.

Latest Patents

Khan is named on one patent, 1 patent: “System and Method for Implementing Variable-Precision Matrix Multiplication Using Low-Precision Digit Matrix Multiplier.” The invention divides large matrices into fixed-size blocks and decomposes those blocks into digit submatrices. It then multiplies, scales, and accumulates the submatrices to support matrix operations with variable precision.

The disclosed system uses a systolic array of block matrix multipliers, each composed of dot-product units. It is designed to handle larger matrix multiplications without substantially increasing latency or wiring congestion. The method also uses unsigned digit multipliers while accounting for signed inputs through adjustments based on row and column sums.

Career Highlights

Khan is associated with Xcelerium Inc. His patent reflects work on hardware methods for carrying out matrix computations efficiently.

Collaborations

Asma Khan and Raheel Khan are identified as Khan’s coworkers. The available information does not specify their roles in the patent or the invention.

Conclusion

Hamza Khan’s patent describes a structured approach to variable-precision matrix multiplication that combines matrix blocking, digit decomposition, and systolic-array hardware.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…