Shanghai, China

Haiying Ji

USPTO Granted Patents = 2 

Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2021

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2 patents (USPTO):Explore Patents

Title: Innovations of Haiying Ji in Integrated Circuit Testing

Introduction

Haiying Ji is a prominent inventor based in Shanghai, China, known for her contributions to the field of integrated circuit (IC) testing. With a total of two patents to her name, she has made significant advancements in the management and testing of ICs, particularly in the context of the industrial internet.

Latest Patents

Haiying Ji's latest patents include an "IC test information management system based on industrial internet" and a "halo test method for an optical chip in an integrated circuit." The first patent discloses an information management method and system for IC tests, which involves providing test data generated by an IC test platform and analyzing it alongside resource data to obtain valuable result data. This innovation aims to enhance the utilization of test data generated during IC tests. The second patent introduces a halo test method for an optical chip, which processes a captured image array into circular patterns to obtain desired values without incurring additional hardware costs. This method addresses the technical challenges associated with testing halo on fingerprint on display (FOD) chips.

Career Highlights

Haiying Ji is currently employed at Sino IC Technology Co., Ltd., where she continues to develop innovative solutions in the field of integrated circuits. Her work has positioned her as a key figure in advancing IC testing methodologies.

Collaborations

Some of her notable coworkers include Bin Luo and Jianhua Qi, who contribute to the collaborative efforts at Sino IC Technology Co., Ltd.

Conclusion

Haiying Ji's innovative patents and contributions to integrated circuit testing reflect her expertise and commitment to advancing technology in this critical field. Her work continues to pave the way for future developments in IC testing methodologies.

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