Haeng Seon Son

Title: Haeng Seon Son: Innovator in Digital Circuit Design

Introduction

Haeng Seon Son is a notable inventor based in Seongnam, South Korea. He has made significant contributions to the field of digital circuit design, particularly in the area of timing modeling methods for latch-based subsystems. His innovative approach has the potential to streamline verification processes in digital circuit design.

Latest Patents

Haeng Seon Son holds a patent for a "Black box timing modeling method and computer system for latch-based subsystem." This patent describes a method for characterizing setup time arcs and clock-to-output delay arcs in digital circuits that include synchronous elements such as latches. The method allows for efficient verification of latch-based designs without the need to re-verify internal components, thereby reducing both verification time and model size.

Career Highlights

Haeng Seon Son is associated with the Postech Academy-Industry Foundation, where he applies his expertise in digital circuit design. His work focuses on enhancing the efficiency of timing modeling methods, which is crucial for the development of advanced digital systems.

Collaborations

He has collaborated with notable colleagues, including Kyung Tae Do and Young Hwan Kim, contributing to various projects that aim to improve digital circuit design methodologies.

Conclusion

Haeng Seon Son's innovative contributions to digital circuit design, particularly through his patented methods, highlight his role as a key figure in the field. His work not only advances technology but also enhances the efficiency of verification processes in digital systems.