Gwo-Sheng Huang

Title: Gwo-Sheng Huang: Innovator in Digital Multiplication Technologies

Introduction

Gwo-Sheng Huang is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of digital multiplication technologies, holding a total of 3 patents. His work focuses on improving the efficiency and functionality of digital multipliers and accumulators.

Latest Patents

Huang's latest patents include a "Parallel-serial multiplier and accumulator" and a "Pipelined parallel-serial architecture for a modified least mean square." The parallel-serial multiplier and accumulator is designed to enhance the process of multiplying a digital multiplicand and a multiplier, resulting in a product that is added to an accumulator input. This innovative design features a recoder, a partial product generator, and a digit serial adder, which collectively improve the efficiency of digital multiplication. The second patent, related to a modified least mean squares adaptive filter, introduces a method where filter coefficients are time-dependent, allowing for modular implementation in VLSI technologies.

Career Highlights

Gwo-Sheng Huang is affiliated with the Industrial Technology Research Institute, where he continues to advance research in digital technologies. His work has been instrumental in developing new methodologies that enhance the performance of digital systems.

Collaborations

Huang has collaborated with notable colleagues, including Her-Ming Jong and Wen-Kuang Su, contributing to various projects that push the boundaries of digital technology.

Conclusion

Gwo-Sheng Huang's innovative patents and contributions to digital multiplication technologies highlight his role as a leading inventor in the field. His work continues to influence advancements in digital systems and VLSI technologies.