Le Touvet, France

Guillaume Chabanne

This inventor holds 5 USPTO granted patents and 1 published patent application and 2 EPO patents. Top assignee: Soitec. Active years: 2017-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Guillaume Chabanne. Retrieved from https://idiyas.com/inventor/guillaume-chabanne

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5 

% Patents Active = 80.0

 

Average Co-Inventor Count = 3.3

ph-index = 1

Forward Citations = 5(Granted Patents)


Location History:

  • Froges, FR (2017)
  • Le Touvet, FR (2020 - 2023)

Company Filing History:


Years Active: 2017-2025

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5 patents (USPTO):Explore Patents

Title: Innovations by Guillaume Chabanne

Introduction

Guillaume Chabanne is a notable inventor based in Le Touvet, France. He has made significant contributions to the field of semiconductor technology, holding a total of five patents. His work focuses on advanced methods for fabricating semiconductor materials, which are crucial for various electronic applications.

Latest Patents

One of his latest patents is a method for fabricating a strained semiconductor-on-insulator substrate. This innovative method involves bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate consists of a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The process includes transferring the monocrystalline semiconductor layer from the donor substrate to the receiving substrate. Trench isolations are then formed to cut a portion from a layer stack that includes the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. This cutting operation results in the relaxation of strain in the strained semiconductor material and applies strain to the transferred monocrystalline semiconductor layer. Prior to the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

Career Highlights

Guillaume Chabanne is currently employed at Soitec, a company renowned for its expertise in semiconductor materials and technologies. His work at Soitec has allowed him to push the boundaries of semiconductor fabrication techniques, contributing to advancements in the industry.

Collaborations

He has collaborated with notable colleagues such as Walter Schwarzenbach and Nicolas Daval, further enhancing the innovative environment at Soitec. Their combined expertise has led to significant developments in semiconductor technology.

Conclusion

Guillaume Chabanne's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence advancements in electronic materials and fabrication methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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