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Years Active: 2016-2018
Title: Gregory Evan Fedynyshyn: Innovator in Cache Coherence Protocols
Introduction
Gregory Evan Fedynyshyn is an accomplished inventor based in Sudbury, MA (US). He has made significant contributions to the field of computer science, particularly in the area of cache coherence protocols. With a total of 2 patents, his work has advanced the efficiency of data management in clustered server environments.
Latest Patents
Fedynyshyn's latest patents focus on systems, methods, and computer program products designed to keep multiple caches updated or coherent across various servers. One of his notable inventions involves a method for receiving a request to write data to a block of a first cache associated with a first server. This method includes identifying a second cache that stores a copy of the block and is associated with a second server. Additionally, it involves transmitting a request to update the second cache with the received write data. Upon receiving a subsequent request to write additional data, the method identifies a third cache for invalidation based on access patterns, which is associated with a third server in the clustered environment.
Career Highlights
Throughout his career, Fedynyshyn has worked with prominent companies in the technology sector. He has been associated with HGST Netherlands, B.V. and Western Digital Technologies, Inc. These experiences have allowed him to apply his innovative ideas in practical settings, contributing to advancements in data storage and management.
Collaborations
Fedynyshyn has collaborated with notable professionals in his field, including Jin Ren and Ken Qing Yang. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.
Conclusion
Gregory Evan Fedynyshyn is a notable inventor whose work in cache coherence protocols has made a significant impact on the technology industry. His patents reflect a commitment to improving data management systems, showcasing his expertise and innovative spirit.